Alignment mark structure and method of fabricating the same

ABSTRACT

An alignment mark structure includes a dielectric layer. A trench is embedded in the dielectric layer. An alignment mark fills up the trench, wherein the alignment mark includes a metal layer covering the trench. A first material layer covers and contacts the metal layer. A second material layer covers and contacts the first material layer. A third material layer covers and contacts the second material layer. The first material layer, the second material layer, and the third material layer independently includes silicon nitride, silicon oxide, tantalum-containing material, aluminum-containing material, titanium-containing material, or a low-k dielectric having a dielectric constant smaller than 2.7, and a reflectance of the first material layer is larger than a reflectance of the second material layer, the reflectance of the second material layer is larger than a reflectance of the third material layer.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to an alignment mark structure and amethod of fabricating the alignment mark structure, and moreparticularly to an alignment mark structure which can provide a highoptical contrast.

2. Description of the Prior Art

In the production of integrate circuit structures, it has becomeincreasingly important to provide structures having a plurality ofcomponents in different material layers due to increasing density of thecircuit elements in the structure. Further, as the device and featuresizes becoming smaller, it is important that the lithography mask bealigned precisely with the wafer during the masking step to minimize themisalignment between the layers.

Alignment marks and the process of aligning alignment marks are keyaspects of fabricating wafers and integrated circuit (IC) chips in themanufacture of semiconductor components. They are key because the chipsthemselves and the devices are fabricated by aligning many intricatelayers of conductors and insulators on a wafer. Typically, the alignmentof one layer with respect to another is accomplished by means of a waferstepper. The wafer stepper is used to project optically a circuitpattern from a lithography mask onto a layer formed on the wafer.However, before the pattern on the lithography mask is transferred, thewafer must first be positioned or aligned precisely with respect to thelithography mask by using the alignment marks already on the wafer. Oncethe alignment is accomplished, the remaining steps of projecting thepattern on to the semiconductor may proceed.

Chemical mechanical polishing (CMP) is a commonly used process in themanufacture of semiconductor wafers. CMP is generally accomplished byremoval of protruding surface topography and a planarized wafer surface.Thus, if features such as alignment marks on the surface of a wafer arenot properly designed and protected from the CMP action, then they canbe damaged or destroyed.

Furthermore, many modern electronic devices contain electronic memoryconfigured to store data, such as magnetic random access memory (MRAM)devices. An MRAM cell includes a magnetic tunnel junction (MTJ) having avariable resistance.

The MTJ's of MRAM devices typically comprise a first magnetic layer(pinned layer), a tunnel insulator formed over the first magnetic layer,and a second magnetic layer (free layer) formed over the tunnelinsulator. Because the first magnetic layer and second magnetic layer ofMTJ's comprise metals, they are opaque, and this makes the stepper can't“see through” the first magnetic layer or the second magnetic layer tolocate the alignment marks.

Therefore, an improved method of aligning the opaque materials to theunderlying alignment mark, and an alignment mark which can avoid thedetrimental effects of CMP are needed.

SUMMARY OF THE INVENTION

In light of the above, the present invention provides a method offabricating the alignment mark structure and a novel alignment markstructure to solve the above-mentioned problem.

According to a preferred embodiment of the present invention, analignment mark structure includes a dielectric layer. A trench isembedded in the dielectric layer. An alignment mark fills up the trench,wherein the alignment mark includes a metal layer covering the trench. Afirst material layer covers and contacts the metal layer. A secondmaterial layer covers and contacts the first material layer. A thirdmaterial layer covers and contacts the second material layer. The firstmaterial layer, the second material layer, and the third material layerare independently comprises silicon nitride, silicon oxide,tantalum-containing material, aluminum-containing material,titanium-containing material, or a low-k dielectric having a dielectricconstant smaller than 2.7, and a reflectance of the first material layeris larger than a reflectance of the second material layer, thereflectance of the second material layer is larger than a reflectance ofthe third material layer.

According to anther preferred embodiment of the present invention, afabricating method of an alignment mark structure includes providing adielectric layer. Next, a trench is formed to be embedded in thedielectric layer. Later, an alignment mark is formed to fill up thetrench, wherein the alignment mark includes a metal layer covering thetrench. A first material layer covers and contacts the metal layer. Asecond material layer covers and contacts the first material layer. Athird material layer covers and contacts the second material layer;wherein the first material layer, the second material layer, and thethird material layer are independently comprises silicon nitride,silicon oxide, tantalum-containing material, aluminum-containingmaterial, titanium-containing material, or a low-k dielectric having adielectric constant smaller than 2.7, and a reflectance of the firstmaterial layer is larger than a reflectance of the second materiallayer, the reflectance of the second material layer is larger than areflectance of the third material layer.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts a wafer with an alignment mark structure thereonaccording to a first preferred embodiment of the present invention.

FIG. 2-8 are schematic drawings illustrating a fabricating process of anMRAM and an alignment mark structure according to a second preferredembodiment of the present invention, wherein:

FIG. 2 depicts a trench and a connection hole formed in a seconddielectric layer;

FIG. 3 depicts a fabricating stage following FIG. 2;

FIG. 4 depicts a fabricating stage following FIG. 3;

FIG. 5 depicts a fabricating stage following FIG. 4;

FIG. 6 depicts a fabricating stage following FIG. 5;

FIG. 7 depicts a fabricating stage following FIG. 6; and

FIG. 8 depicts a fabricating stage following FIG. 7.

FIG. 9 depicts a fabricating method according to a reference embodimentof the present invention.

FIG. 10 depicts simulation results of reflectance vs. wavelength ofsample 1 and sample 2.

DETAILED DESCRIPTION

FIG. 1 depicts a wafer with alignment mark structures thereon accordingto a first preferred embodiment of the present invention. As shown inFIG. 1, a wafer 10 is provided. A device region 12 (marked by a boldframe) and an edge region 14 are defined on the wafer 10. In the deviceregion 12, there may be several die regions 16, and each of the dieregions 16 has memory cells 18 form thereon. The memory cells 18 may beMRAM arrays or RRAM (resistive random access memory) arrays, etc. In theedge region 14, there may be unused or may have incomplete die regions20 formed on them. Scribe lines 22 are respectively arranged between thedie regions 16/20. An alignment mark structure 50 is disposed on thewafer 10. The alignment mark structure 50 may be disposed in at leastone of the die regions 16 within the device region 12. In anotherexemplary case, the alignment mark structure 50 may be disposed in atleast one of the die regions 20 within the edge region 14. In yetanother exemplary case, the alignment mark structure 50 may be disposedin at least one of the scribe lines 22. Although the alignment markstructures 50 in FIG. 1 are disposed in the device region 12, the edgeregion 14 and the scribe line 22 at the same time, based on differentrequirements, the alignment mark structures 50 can be positioned only inone or two regions selected from the device region 12, the edge region14 and the scribe line 22. For example, the alignment mark 50 structureis disposed only in the device region 12.

The shape of the alignment mark structure 50 is exemplified as a set ofrectangles; however, based on different product requirements, the shapeof the alignment mark structure 50 could be other shapes such as a crossor a circle, etc.

FIG. 2-8 are schematic drawings illustrating a fabricating process of anMRAM and an alignment mark structure according to a second preferredembodiment of the present invention.

As shown in FIG. 1 and FIG. 2, an insulation layer 26 is provided, andan interconnection structure 28 a is formed in the insulation layer 26.The insulation layer 26 may be disposed on the wafer 10. A memory cellregion R1 and an alignment mark region R2 are defined on the insulationlayer 10. The memory cell region R1 is arranged in each of the dieregions 16 and memory cells 18 will be formed in the memory cell regionR1. The alignment mark region R2 may be in the device region 12, theedge region 14 or the scribe line 22.

An MRAM subsequently formed on the interconnection structure 28 a may beelectrically connected to other devices via the interconnectionstructure 28 a and/or other connection structures, but not limitedthereto.

A first dielectric layer 30 and a second dielectric layer 32 may besequentially formed covering the insulation layer 26 and theinterconnection structure 28 a. The first dielectric layer 30, and thesecond dielectric layer 32 may respectively tetraethoxysilane (TEOS),boron phospho-silicate glass (BPSG), silicon oxynitride, silicon oxide,silicon nitride or other suitable materials.

A connection hole 34 may be formed penetrating the first dielectriclayer 30 and the second dielectric layer 32 on the interconnectionstructure 28 a for exposing a part of the interconnection structure 28a, and a trench 36 may be formed penetrating the first dielectric layer30 and the second dielectric layer 32 on the alignment mark region R2for exposing a part of the insulation layer 26. In some embodiments, theconnection hole 34 and the trench 36 may be formed concurrently by thesame process.

Later, a barrier 38 is formed to conformally cover and contact theconnection hole 34, the trench 36, the first dielectric layer 30 and thesecond dielectric layer 32. Next, a metal layer 40 is formed toconformally cover and contact the barrier 38. Now, the metal layer 40and the barrier 38 fill up the connection hole 34. The metal layer 40and the barrier 38 within the connection hole 34 serve as anotherinterconnection structure 28 b. Subsequently, a first material layer 42is formed to conformally cover and contact the metal layer 40 and fillsin the trench 36. After that, a second material layer 44 is formed toconformally cover and contact the first material layer 42. Finally, athird material layer 46 is formed to conformally cover and contact thesecond material layer 44. The depth of the trench 36 is preferablybetween 300 angstroms and 800 angstroms. As shown in FIG. 4, a chemicalmechanical polishing (CMP) is performed to planarize the third materiallayer 46, the second material layer 44, the first material layer 42, themetal layer 40 and the barrier 38 to entirely remove the third materiallayer 46, the second material layer 44, the first material layer 44, themetal layer 40 and the barrier 38 outside of the trench 38, and toremove the metal layer 40 and the barrier 38 outside of the connectionhole 34.

Moreover, a top surface of each of two ends of the metal layer 40 isaligned with the top surface of the second dielectric layer 32. A topsurface of each of two ends of the first material layer 42 is alignedwith the top surface of the second dielectric layer 32. A top surface ofeach of two ends of the second material layer 44 is aligned with the topsurface of the second dielectric layer 32. A top surface of the thirdmaterial layer 46 is aligned with the top surface of the seconddielectric layer 32.

After the chemical mechanical polishing, the remaining third materiallayer 46, the second material layer 44, the first material layer 42, themetal layer 40 and the barrier 38 in the trench 36 form an alignmentmark 48. Now, an alignment mark structure 50 of the present invention iscompleted.

As shown in FIG. 5, a bottom electrode material 52 is formed to coverthe alignment mark structure 50, the interconnection structure 28 b andthe second dielectric layer 32. As shown in FIG. 6, the bottom electrodematerial 52 is planarized to decrease the thickness of the bottomelectrode material 52. Later, a memory material 54 and a hard maskmaterial 56 are formed in sequence to cover the bottom electrodematerial 52.

As shown in FIG. 7, part of the hard mask material 56, part of thememory material 54 and part of the bottom electrode material 52 withinthe alignment mark region R2 are removed so as to expose the alignmentmark structure 50. Later, a patterned photoresist layer 58 is formedwithin the device region R1 to define the position of an MRAM which willbe formed later. The alignment mark structure 50 is used to align thelithography mask 60 by a stepper and then the patterned photoresistlayer 58 is formed through a lithography process.

As shown in FIG. 8, the hard mask material 56, the memory material 54and the bottom electrode material 52 are patterned to become a hard mask56 a, a MTJ film 54 a and a bottom electrode 52 a. The hard mask 56 a,the MTJ film 54 a and the bottom electrode 52 a form an MRAM 62.

The hard mask 56 a may include insulation materials such as siliconnitride, silicon oxynitride, or other suitable insulation materials orconductive materials. In some embodiments, The MTJ film 54 a may includea pinned layer, a tunnel insulator, a free layer, a barrier layer, and aconductive layer sequentially stacked with one another. The componentsof the MTJ film 54 a may be modified and/or include other materiallayers according to other design considerations. The pinned layer in theMTJ film 54 a may include antiferromagnetic materials such as ironmanganese (FeMn) or cobalt/platinum (Co/Pt) multilayer, but not limitedthereto. The free layer in the MTJ film may include ferromagneticmaterials such as cobalt, iron (Fe), cobalt-iron (CoFe),cobalt-iron-boron (CoFeB), or other suitable ferromagnetic materials.The tunnel insulator and the barrier layer in the MTJ film 54 a mayinclude insulation materials such as magnesium oxide (MgO), aluminumoxide, or other suitable insulation materials. The material of theconductive layer in the MTJ film 54 a may be metallic materials, such astantalum, tantalum nitride, platinum (Pt), ruthenium (Ru). The materialof the conductive layer in the MTJ film 54 a may be similar to thematerial of the bottom electrode 52 a, but not limited thereto.

The alignment mark structure 50 of the present invention is suitable foraligning a lithography mask when there is an opaque material layer suchas magnetic materials within the MTJ film on the wafer 10.

As shown in FIG. 4, the alignment mark structure 50 includes aninsulation layer 26, a first dielectric layer 30, and a seconddielectric layer 32. A trench 36 is embedded in the second dielectriclayer 32, the first dielectric layer 30 and the insulation layer 26. Thedepth of the trench 36 is preferably between 300 angstroms and 800angstroms. An alignment mark 48 fills up the trench 36. A top surface ofthe alignment mark 48 is aligned with a top surface of the seconddielectric layer 32. In details, the alignment mark 48 includes abarrier 38, a metal layer 40, a first material layer 42, a secondmaterial layer 44 and the third material layer 46. The barrier 38, themetal layer 40, the first material layer 42, the second material layer44 and the third material layer 46 are disposed from bottom to top. Morespecifically speaking, the barrier 38 contacts and conformally coversthe trench 36. The metal layer 40 covers the trench 36 and contacts thebarrier 38. The first material layer 42 covers and contacts the metallayer 40. The second material layer 44 covers and contacts the firstmaterial layer 42. The third material layer 46 covers and contacts thesecond material layer 44.

The first material layer 42 includes silicon nitride, silicon oxide,tantalum-containing material, aluminum-containing material,titanium-containing material, or a low-k dielectric having a dielectricconstant smaller than 2.7. The second material layer 44 includes siliconnitride, silicon oxide, tantalum-containing material,aluminum-containing material, titanium-containing material, or a low-kdielectric having a dielectric constant smaller than 2.7. The thirdmaterial layer 46 includes silicon nitride, silicon oxide,tantalum-containing material, aluminum-containing material,titanium-containing material, or a low-k dielectric having a dielectricconstant smaller than 2.7. The first material layer 42, the secondmaterial layer 44 and the third material layer 46 can be the same ordifferent based on different product requirements.

The tantalum-containing material includes tantalum nitride. Thetitanium-containing material includes titanium nitride. Thealuminum-containing material includes aluminum oxide. The low-kdielectric includes fluorinated silicate glass. The metal layer 40 maybe tungsten, copper or aluminum. According to a preferred embodiment ofthe present invention, a thickness of the third material layer 46 islarger than a thickness of the second material layer 44 and is alsolarger than a thickness of the first material layer 42. The thickness ofthe metal layer 40 is preferably larger than the thickness of the thirdmaterial layer 46. According to a preferred embodiment of the presentinvention, the total thickness of the barrier 38 is between 50 and 400angstroms and the barrier 38 can be a multi-layer film stack. Thethickness of the metal layer 40 is preferably between 300 and 800angstroms. The thickness of the first material layer 42 is preferablygreater than 80 angstroms. The thickness of the second material layer 44is preferably greater than 80 angstroms. The thickness of the thirdmaterial layer 46 is preferably between 20 angstroms and 150 angstroms.

However, based on different product requirements, the thicknesses of themetal layer 40, the first material layer 42, the second material layer44, the third material layer 46 can be altered. The thickness of thethird material layer 46 does not necessarily be the largest among thethree material layers. It could be the thickness of the second materiallayer 44 larger than the thickness of the third material layer 46 forexample. Furthermore, in yet another embodiment, the thickness of themetal layer 40 doesn't have to be the largest thickness among thealignment mark 48.

It is noteworthy that a reflectance of the first material layer 42 islarger than a reflectance of the second material layer 44, thereflectance of the second material layer 44 is larger than a reflectanceof the third material layer 46. In other words, the respectivereflectance of the first material layer 42, the second material layer 44and the third material layer 46 are arranged from large to small along adirection away from the metal layer 40. For example, the first materiallayer 42 is nearer to the metal layer 40 and the third material layer 46is farther from the metal layer 40; therefore, the reflectance of thefirst material layer 42 is larger than that of the third material layer46.

According to a preferred embodiment of the present invention, the firstmaterial layer 42 is titanium nitride. The second material layer 44 issilicon nitride. The third material layer 46 is silicon oxide. The metallayer 40 is tungsten, and the barrier 38 is a multi-layer film stackincluding titanium and titanium nitride.

The special arrangement of the reflectance of the first material layer42, the second material layer 44 and the third material layer 46 makesthe alignment mark 48 has a reflectance not greater than 0.3. Therefore,comparing to the second dielectric layer 32, the alignment mark 48 has amuch smaller reflectance. In this way, when the stepper projects a laserto detect the alignment mark 48, the contrast between the alignment mark48 and the second dielectric layer is enhanced because of the smallreflectance of the alignment mark 48. Therefore, the stepper can locatethe position of the alignment mark 48 more precisely.

Furthermore, although in the second preferred embodiment there are onlythree material layers in the alignment mark 48, however, there can bemore than three material layers in the alignment mark 48. No matter howmany the material layers in the alignment mark 48, they have to bearranged with a reflectance from large to small along a direction awayfrom the metal layer 40.

FIG. 9 depicts a fabricating method according to a reference embodimentof the present invention, wherein elements which are substantially thesame as those in the embodiment of FIG. 4 are denoted by the samereference numerals; an accompanying explanation is therefore omitted.

The difference between the fabricating steps in FIG. 9 and FIG. 4 isthat the first material layer 42, the second material layer 44 and thethird material layer 46 are not formed in the FIG. 9. As shown in FIG.9, during the chemical mechanical polishing, the metal layer 40 is notcovered by the first material layer 42. Therefore, after the chemicalmechanical polishing, the edge of the metal layer 40 and the barrier 38are damaged, and some recesses 60 are formed at the edge of the metallayer 40 and the barrier 38. Theses recesses 60 may influence theoptical contrast of an alignment mark formed afterwards.

After the chemical mechanical polishing, the second dielectric layer 32,the barrier 38, and the metal layer 40 form an alignment mark structure150 in FIG. 9. However, because the trench 36 is not filled up duringthe chemical mechanical polishing, some slurry residues 62 of thechemical mechanical polishing may remain on the surface of the metallayer 40 because there is still an opening on the trench 36. Theseslurry residues 62 will influence the attachment ability of the materiallayers formed afterwards.

Comparing to the fabricating method of the reference embodiment, thefirst material layer 42, the second material layer 44 and the thirdmaterial layer 46 of the second preferred embodiment of the presentinvention fill up the trench 36, therefore there is no opening duringthe chemical mechanical polishing. In this way, slurry residues 62 won'tremain on the surface of the metal layer 40 and the recess 60 can beavoided after the chemical mechanical polishing.

FIG. 10 depicts simulation results of reflectance vs. wavelength ofsample 1 and sample 2.

As shown in FIG. 4 and FIG. 10, sample 1 is an alignment mark structurewith a structure shown in FIG. 4. In the alignment mark structure ofsample 1, the barrier 38 consists of titanium with a thickness of 140angstroms and titanium nitride with a thickness of 30 angstroms. Thethickness of the metal layer 40 is 400 angstroms. The thickness of thefirst material layer 42 is 100 angstroms. The thickness of the secondmaterial layer 44 is 100 angstroms. The thickness of the third materiallayer 46 is 100 angstroms. The metal layer 40 is tungsten. The firstmaterial layer 42 is titanium nitride. The second material layer 44 issilicon nitride. The third material layer 46 is silicon oxide.

As shown in FIG. 9 and FIG. 10, sample 2 is an alignment mark structurewith a structure shown in FIG. 9. In the alignment mark structure ofsample 2, the barrier 38 consists of titanium with a thickness of 140angstroms and a titanium nitride with thickness of 30 angstroms. Thethickness of the metal layer 40 is 400 angstroms. The metal layer 40 istungsten.

The reflectance of alignment marks of sample 1 and sample 2 aresimulated in several wavelengths such as 200 nm, 400 nm 600 nm and 800nm and at an incident illumination angle in 90 degrees. As shown in FIG.10, the reflectance of alignment mark of sample 2 is greater than 0.4.The reflectance of alignment mark of sample 1 is not greater than 0.3.Therefore, comparing to the alignment mark of sample 2, the alignmentmark of sample 1 can offer a smaller reflectance, and provides a bettercontrast for the stepper.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. An alignment mark structure, comprising: analignment mark, comprising: a dielectric layer; a trench embedded in thedielectric layer; an alignment mark filling up the trench, wherein thealignment mark comprises: a metal layer covering the trench; a firstmaterial layer covering and contacting the metal layer; a secondmaterial layer covering and contacting the first material layer; and athird material layer covering and contacting the second material layer,wherein the first material layer, the second material layer, and thethird material layer independently comprises silicon nitride, siliconoxide, tantalum-containing material, aluminum-containing material,titanium-containing material, or a low-k dielectric having a dielectricconstant smaller than 2.7, and a reflectance of the first material layeris larger than a reflectance of the second material layer, thereflectance of the second material layer is larger than a reflectance ofthe third material layer.
 2. The alignment mark structure of claim 1,wherein the metal layer comprises tungsten, copper, or aluminum.
 3. Thealignment mark structure of claim 1, wherein the first material layer istitanium nitride, the second material layer is silicon nitride, thethird material layer is silicon oxide, and the metal layer is tungsten.4. The alignment mark structure of claim 1, wherein a reflectance of thealignment mark is not greater than 0.3.
 5. The alignment mark structureof claim 1, wherein a top surface of the alignment mark is aligned witha top surface of the dielectric layer.
 6. The alignment mark structureof claim 1, wherein a thickness of the third material layer is largerthan a thickness of the second material layer, the thickness of thethird material layer is larger than a thickness the first materiallayer.
 7. A fabricating method of an alignment mark structure,comprising: providing a dielectric layer; forming a trench embedded inthe dielectric layer; forming an alignment mark filling up the trench,wherein the alignment mark comprises: a metal layer covering the trench;a first material layer covering and contacting the metal layer; a secondmaterial layer covering and contacting the first material layer; and athird material layer covering and contacting the second material layer;wherein the first material layer, the second material layer, and thethird material layer independently comprises silicon nitride, siliconoxide, tantalum-containing material, aluminum-containing material,titanium-containing material, or a low-k dielectric having a dielectricconstant smaller than 2.7, and a reflectance of the first material layeris larger than a reflectance of the second material layer, thereflectance of the second material layer is larger than a reflectance ofthe third material layer.
 8. The fabricating method of the alignmentmark structure of claim 7, wherein steps of fabricating the alignmentmark comprises: forming the metal layer covering the trench and thedielectric layer; forming the first material layer covering the metallayer; forming the second material layer covering the first materiallayer; forming the third material layer covering the second materiallayer; and planarizing the metal layer, the first material layer, thesecond material layer, the third material layer to entirely remove themetal layer, the first material layer, the second material layer, thethird material layer outside of the trench.
 9. The fabricating method ofthe alignment mark structure of claim 7, wherein the metal layercomprises tungsten, copper, or aluminum.
 10. The fabricating method ofthe alignment mark structure of claim 7, wherein the first materiallayer is titanium nitride, the second material layer is silicon nitride,the third material layer is silicon oxide, and the metal layer istungsten.
 11. The fabricating method of the alignment mark structure ofclaim 7, wherein a reflectance of the alignment mark is not greater than0.3.
 12. The fabricating method of the alignment mark structure of claim7, wherein a thickness of the third material layer is larger than athickness of the second material layer, the thickness of the thirdmaterial layer is larger than a thickness of the first material layer.13. The fabricating method of the alignment mark structure of claim 7,further comprising: after forming the alignment mark, forming a bottommaterial, a memory material and a hard mask material in sequence andcovering the dielectric layer; forming a patterned photoresist by usingthe alignment mark to align a lithography mask; and patterning thebottom material, the memory material and the hard mask material bytaking the patterned photoresist as a mask to form an MRAM.